1. Field of the Invention
The present invention relates to a semiconductor device and more particularly, to a flash memory device and a method for fabricating the same.
2. Discussion of the Related Art
A flash memory device is a nonvolatile memory device. Depending on a cell array configuration, the flash memory device may be formed as a NAND flash device, which requires no contact pattern to connect each cell transistor, or a NOR flash device, which has contact patterns for each cell transistor. NAND flash memory, which uses serially configured cell transistors, i.e., a cell string, provides no random access capability but, without the contact patterns, is more suitable for forming highly integrated (mass storage) devices. By contrast, NOR flash memory enables random access but, due to a contact pattern formation for each cell transistor, is less desirable for embodying highly integrated memory devices.
FIGS. 1A-1C illustrate a conventional flash memory device. FIG. 1B is a cross-sectional view through line B-B of FIG. 1A, and FIG. 1C is a cross-sectional view through line C-C of FIG. 1A. A device isolation film 12 is formed on a semiconductor substrate 10 to define a plurality of active regions. A plurality of floating gates 16 are formed above the active regions by interposing a tunnel insulating film 14. The device isolation film 12 defines a plurality of striped-shaped active regions in the semiconductor substrate 10. The floating gates 16 are arranged on the respective active regions to be spaced apart from one another. A control gate electrode 20 is formed above each floating gate 16 to cross each active region. A gate interlayer dielectric film 18 is interposed between the floating gate 16 and the control gate electrode 20. The floating gate 16 is electrically insulated from the substrate 10 and the control gate electrode 20 by the tunnel insulating film 14 and the gate interlayer dielectric film 18. Source/drain regions 22s and 22d, which include implanted impurities, are formed in the active region at both sides of the floating gate 16. As shown, the flash memory device has a gate structure in which the floating gate 16, the gate interlayer dielectric film 18, and the control gate electrode 20 are sequentially deposited and then commonly patterned together with the tunnel insulating film 14. Spacers 24 are formed at sidewalls of the gate structure during a junction engineering of a peripheral circuit and to electrically isolate the gate structure from a line structure (not shown).
As described above, since the control gate electrode 20 is patterned by a photo-etching process, cell array integration is restricted by the line-width limit (minimum feature size) of a photolithographic process, which may be in the tens of nanometers. Moreover, short channel effects become serious considerations when such narrow line widths are associated with the gate electrode. For these reasons, there are limitations in using photolithography to form the gate structure of the cell transistor of a flash memory device.